A PCI Express link is built from one or more lanes, and each lane is a pair of differential signals, one for transmit and one for receive. Before any data moves, the two ends run the LTSSM, a state machine that trains the link, checks the width and speed, and only then hands it over to the data link layer. The PIPE interface is the boundary between that logic and the physical layer hardware, and it is where many of the timing details become visible.
How do PCI Express lanes work?
A lane is not a bus in the old sense. It carries a serial bit stream in each direction at the same time, so a single lane is already full duplex. The transmitter sends a clock embedded in the data, and the receiver recovers it, which is why a lane needs no separate clock wire and why skew between lanes has to be handled at the receiver rather than at the source.
A link can be one, two, four, eight, sixteen or thirty-two lanes wide. The width is negotiated during training, and both ends must agree on it. A device that supports sixteen lanes can come up as eight or four if the slot, the connector or the other end cannot support more. This is why a card in a shorter slot still works, but with less aggregate bandwidth.
Lanes are grouped into a link, and the link is what the configuration space describes. Each link has its own set of registers for width, speed and status. The operating system sees a device at the end of a link, not the individual lanes, so the lane count is a property of the path rather than of the device alone.
For a closer reading of how lanes, root ports and switches are described in the specification, the notes at PCI Express lanes set out the link layer and topology material from the public documents. That reading desk is aimed at people who want the numbers and the revision notes rather than a summary.
What happens during LTSSM link training?
The LTSSM, the Link Training and Status State Machine, is the sequence every link follows from power-on to normal operation. It starts in Detect, where the receiver looks for a far-end termination. If nothing is present, the link stays there. If a receiver is detected, the state machine moves to Polling, where the two ends exchange training sequences to establish bit lock and symbol lock.
Polling is followed by Configuration. In this state the two ends agree on the link number, the lane numbers and the width. Lanes that do not train correctly can be dropped, and the link comes up narrower. This is the stage where a link may fall back from sixteen lanes to eight, or from eight to four, without any error being reported to the operating system beyond the final width.
Once the width is set, the link moves to L0, the normal operating state. From L0 it can enter low-power states such as L1 and L2, and it can return to recovery if the signal quality degrades. Recovery re-runs part of the training without a full reset, which is how a link can adapt to a change in temperature or a marginal connector.
The speed is negotiated separately from the width. A link can train at a lower speed first and then move up, or it can stay at the lower speed if the higher one does not train. The LTSSM does not decide the speed on its own; it follows the capabilities advertised by both ends and the result of the equalisation process.
What is the PIPE interface in PCI Express?
The PIPE interface, the Physical Interface for PCI Express, is the standard boundary between the media access logic and the physical layer. It defines the signals, the clocking and the handshake that a controller uses to talk to a SerDes or a PHY block. It is not a wire protocol on the board; it is an internal interface, and it is specified so that a controller from one vendor can be paired with a PHY from another.
PIPE carries the transmit and receive data, the status of the receiver, the power state and the control signals for the LTSSM. It also carries the results of the receiver detection and the equalisation handshake. When a link fails to train, the PIPE status registers are often the first place where the reason is visible, because they show which state the physical layer reached.
Different versions of PIPE correspond to different generations of the link. The width of the data path and the clocking change with the speed, so a design for one generation does not map directly onto another. This is one reason why a controller and a PHY must be checked for PIPE version compatibility before they are used together.
Speeds, encodings and usable bandwidth by generation
Each generation of PCI Express has a defined signalling rate and an encoding scheme, and the usable bandwidth is lower than the raw rate because of that encoding and because of the protocol overhead.
Generation 1 runs at 2.5 GT/s with 8b/10b encoding. The encoding adds two bits for every eight, so the usable rate is about 2 Gbit/s per lane per direction. Generation 2 runs at 5 GT/s with the same 8b/10b encoding, giving about 4 Gbit/s per lane per direction.
Generation 3 runs at 8 GT/s and changes to 128b/130b encoding. The overhead is much smaller, so the usable rate is close to 8 Gbit/s per lane per direction. Generation 4 runs at 16 GT/s with the same 128b/130b encoding, and Generation 5 runs at 32 GT/s, again with 128b/130b. Generation 6 runs at 64 GT/s and uses PAM4 signalling with forward error correction, which changes the relationship between the raw rate and the usable rate.
The numbers quoted for a slot are usually the raw rate multiplied by the lane count. A sixteen-lane Generation 3 link is often described as about 128 Gbit/s, but the usable figure after encoding and protocol overhead is lower. For planning, the usable figure is the one that matters, and it is the one that appears in the tables of the specification.
Why the width and speed are negotiated, not fixed
A link does not assume its final width and speed at power-on. It discovers them. This is what allows a card to work in a slot with fewer lanes, and it is what allows a system to fall back when a connector or a trace is marginal. The cost is that the final state is not always the one the label on the box suggests.
When a link comes up narrower or slower than expected, the LTSSM history and the PIPE status are the places to look. A link that trains at Generation 1 on a Generation 3 slot is usually a signal integrity problem, not a configuration error. A link that trains at half width is usually a lane that failed during Configuration. Both are reported, but not always in the same place.
Reading the specification without the marketing
The public specifications describe the link in terms of states, registers and timing. They do not describe it in terms of the numbers on a retail box. For anyone who needs to check a design or explain a fallback, the useful material is the state machine, the encoding tables and the equalisation procedure.
A reading desk that works from those documents, with dated revision notes, is more useful than a summary that omits the conditions. The figures for each generation only make sense alongside the encoding and the overhead, and the LTSSM only makes sense alongside the states that precede and follow it. Read together, they explain why a link behaves the way it does at power-on.